Priyadarsan Patra

Priyadarsan Patra

Intel Corporation, JF5-254, 2111 N.E. 25th Ave., Hillsboro, OR 97124, USA

E-mail: priyadarsan.patra at intel.com or ppatra at ieee.org

Phone: 503-264-8258

Short Biography:

Dr. Priyadarsan “Darshan” Patra is a lead architect and scientist responsible for pre-silicon and post-silicon validation/survivability a flagship processor of Intel. He developed domino circuit synthesis and power-noise tradeoff optimization for P4 class of processors. He architected and co-designed probeless post-silicon debug capability for servers. A founding member of Validation Research Lab of Intel, he led research efforts in run-time validation, resilient architecture, and early design exploration of networks-on-chip. He has co-authored a recent book on low-power design/synthesis and has received two conference best-paper nominations.

Darshan serves on the committees of several IEEE conferences and mentors through SRC, GSRC programs. He is elected Senior Member of the ACM and the IEEE. He is on the editorial board and board of governors of several academic institutions.

Priyadarsan shares a deep and joyous passion for sustainable and equitable development and for inventing and using technology for social progress. He is Founding Chair of the Sustainable Economic and Educational Development Society (SEEDS). Social activism dates back to his college days when he co-founded India Progressive Action Group in Austin where it won Best Student organization award for leadership in socio-political issues affecting South Asians. Believing in the great importance of being involved in local community, he has taught Portland-area kids for a few years as a coach. He is a United-way Ambassador and an Intel-Involved volunteer.

Education:

Ph.D. (Computer Sciences), University of Texas at Austin
M.S. (Computer & Information Sciences), University of Massachusetts at Amherst, MA.
B.Engg. (Electronics and Telecommunication Engg.), Indian Institute of Science, Bangalore

Some Honors and Recognitions:

Founding Chair of the Sustainable Economic and Educational Development Society (SEEDS) www.seedsnet.org

Intel Hero Award, 2010

Trail Blazer Award for break-through technology for synthesis of domino circuits and piloting it on Intel's flagship product

Distinguished Young Leader Award: Highest honor presented annually by Orissa Society of the Americas to a person with demonstrated superior leadership and achievement. 1999.

Seven Patents issued or pending

Authored over 35 scholarly papers/articles and a recent graduate-level textbook on Low-power VLSI

Multiple Divisional Recognitions from Intel Corp.

Editor, Journal of Computing

Elected Senior Member of the Association for Computing Machinery, 2008.

Elected Senior Member of the Institute of Electrical & Electronics Engineers, 2005

Founding General Chair, International Symposium on Electronic System Design

Program Committee Member and Oraganizing Chair for several national academic conferences and industry consortia in Computer Science and Engineering area

Scientist and Architect, Intel Corp.

Five Divisional Awards (Intel Corp)

Member of Board of Governors of KMBB College of Engineering and Technology, and Advisor, Human Development Foundation, India

Vice-Chair, IEEE Oregon (2009-10)

Co-Chair, Logic Validation and Debug, Intel's world-wide conference: Design Technology and Test Conf. 2010

Industry Member on the review board of the Global Research Collaboration/Semiconductor Research Center.

Student Fellowships held: Oxford University; Microelectronics and Computer Development; Center for Computer Engineering Research

2007-09 Secretary of the Odisha Society of the Americas

United Way Ambassador and Corporate Services Award Winner

Mathcounts Coach at Stoller Middle School -- several Coach and Team Awards

Technology Advisor, Indo-American Medical Association of Oregon 2008-09

Selected Publications:

Book: S. P. Mohanty, N. Ranganathan, E. Kougianos, Priyadarsan Patra. “Low-Power High-Level Synthesis for Nanoscale CMOS Circuits”. Springer Verlag, Feb. 2008.
Kougianos, Mohanty and Patra. "Digital Nano-CMOS VLSI Design Courses in Electrical and Computer Engineering Through Open-Source/Free Tools", Invited Workshop at ISED2010
Garitselov, Kougianos, Mohanty and Patra. "Nano-CMOS Mixed-Signal Circuit Metamodeling Techniques: A Comparative Study", to appear at IEEE Int'l Symposium on Electronic System Design, 2010
Priyadarsan Patra, et al., Validation Control Unit, Design, Test and Technology Conference (DTTC), Intel 2010
Priyadarsan Patra, et al., Enabling Probeless PSMI for Wesmere Server, DTTC, Intel 2009
Ghai, Patra et al. A PVT aware accurate statistical logic library for high-k metal-gate nano-CMOS, International Symposium on Quality Electronic Design 3/16/2009
Mohanty, Patra, et al. A Combined Packet Classifier and Scheduler Towards Net-Centric Multimedia Processor Design, International Conference on Consumer Electronics 1/14/2009.
K. Chen, S. Malik and P. Patra. Runtime Validation of Memory Ordering Using Constraint Graph Checking. High Performance Computer Architecture, HPCA 2008.
Bin Li, P. Patra and L. Peh. Network-on-chip modeling and estimation under process and temperature variation. 2nd IEEE International Symposium on Networks-on-Chip (NOCS 2008).
K. Chen, S. Malik and Priyadarsan Patra. Runtime Validation of Transactional Memory Systems. Int'l Symposium on Quality Electronic Design (ISQED) 2008.
S. Mohanty, E. Kougianos, and P. Patra. “Process Variation Aware Simultaneous Leakage and Dynamic Power Minimization during Nano-CMOS Behavioral Synthesis.” Revised for IEEE Trans. on CAD.
S. Mohanty, E. Kougianos, D. Ghai and P. Patra. “Interdependency Study of Process and Design Parameter Scaling for Power Optimization of Nano-CMOS Circuits Under Process Variation.” IWLS 2007.
Priyadarsan Patra. On the Cusp of a Validation Wall. Invited Article for IEEE Design & Test Magazine. 2007.
Min Pan, Priyadarsan Patra and Chris Chu. A Novel Performance-Driven Topology Design Algorithm. 12th Asia and South Pacific Design Automation Conference. ASP-DAC 2007.
Priyadarsan Patra, Charles E. Dike, Nasser A. Kurd, and Javed Barkatullah. A mesh-based clock deskew scheme and its formal correctness.
Kavel Buyuksahin, Priyadarsan Patra, and Farid Najm. Estima: An architectural-level power estimator for multi-ported pipelined register files. In Proc. Int’l Symposium On Low Power Electronics and Design, 2003.
Charles E. Dike, Nasser A. Kurd, Priyadarsan Patra, and Javed Barkatullah. A design for digital, dynamic clock deskew. In Symposia on VLSI Technology and Circuits, 2003.
B. Chappell, X. Wang, P. Patra, et al. A system-level solution to domino synthesis with 2 GHz application. In Proc. International Conf. Computer Design (ICCD), October 2002.
Priyadarsan Patra, Unni K. Narayanan, and Taewhan Kim. Phase assignment for synthesis of low power domino circuits. ACM Transactions on Design Automation of Electronic Systems. (Submitted for publication).
Priyadarsan Patra. Power issues in ULSI circuits. In International Conference on Information Technology, December 2000.
Mahesh Ketkar, Sachin Sapatnekar, and Priyadarsan Patra. Convexity-based optimization for power-delay tradeoff using transistor sizing. In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2000.
Priyadarsan Patra. Estima: An architecture-level estimator for multi-ported multi-cycle register files. Technical report, Intel Corp., December 2002. Strategic CAD Labs technology.
Priyadarsan Patra and Xinning Wang. Overview of DCAL logic and timed synthesis. Technical report, Intel Corp., December 2001. Strategic CAD Labs Technology Report.
B. Chappell, X. Wang, P. Patra, J. Vendrell, S. Rangavirsan, S. Otto, and E. Zahavi. DCAL domino design techniques for efficient synthesis of correct, high speed control logic. In Design and Test Technology Conference (Intel Corp.), 1997.
Priyadarsan Patra and Unni K. Narayanan. Automated phase assignment for the synthesis of low power domino circuits. In Proc. ACM/IEEE Design Automation Conference, June 1999.
Priyadarsan Patra, Unni K. Narayanan, and Taewhan Kim. Phase assignment for synthesis of low power domino circuits. In Electronics Letters, June 2001.
Priyadarsan Patra, Stanislav Polonsky, and Donald S. Fussell. Delay insensitive logic for RSFQ superconductor technology. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 1997

Selected Patents:

Priyadarsan Patra. A method of non-intrusive, low-cost, high-bandwidth piggyback debug chip with value add..
Priyadarsan Patra. Spatial Curvature Techniques for Multiobjective Routing Optimization.
Priyadarsan Patra. Technique for High Fidelity and Efficient Random Number Generation.
Priyadarsan Patra. A method to reduce network costs and its application to domino circuits. US Patent# 6529861.
Priyadarsan Patra and Unni K. Narayanan. Phase optimization for low power domino circuits. US Patent # 6556962.
Priyadarsan Patra and Barbara Chappell. Timed synthesis for power optimization of high performance circuits. US Patent# 6721924.
Priyadarsan Patra. Smart Checker ALU for Dynamically Validating Architectures. Patent Pending.

Graduate Student Supervision: Ph.D. committee member or co-advisor to students at Univ. of Illinois, Urbana Champaign, and the University of Minnesota and the Princeton University.

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